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| Freescale Semiconductor Data Sheet: Advance Information MCF5208EC Rev. 0.5, 3/2006 MCF5208 ColdFire(R) Microprocessor Data Sheet Supports MCF5207 & MCF5208 by: Microcontroller Division The MCF5207 and MCF5208 devices are highly-integrated 32-bit microprocessors based on the version 2 ColdFire microarchitecture. Both devices contain a 16-Kbyte internal SRAM, an 8-Kbyte configurable cache, a 2-bank SDR/DDR SDRAM controller, a 16-channel DMA controller, up to three UARTs, a queued SPI, a low-power management modeule, and other peripherals that enable the MCF5207 and MCF5208 for use in industrial control and connectivity applications. The MCF5208 device also features a 10/100 Mbps fast ethernet controller. This document provides detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MCF5207 and MCF5208 microprocessors. It was written from the perspective of the MCF5208 device. See the following section for a summary of differences between the two devices. Table of Contents 1 2 3 4 5 6 MCF5207/8 Device Configurations......................2 Ordering Information ...........................................3 Signal Descriptions..............................................3 Mechanicals and Pinouts ....................................8 Preliminary Electrical Characteristics ................18 Revision History ................................................43 This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. * Preliminary MCF5207/8 Device Configurations 1 MCF5207/8 Device Configurations Table 1. MCF5207 & MCF5208 Configurations Module Version 2 ColdFire Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral and External Bus Clock (Core clock / 2) Performance (Dhrystone/2.1 MIPS) Instruction/Data Cache Static RAM (SRAM) SDR/DDR SDRAM Controller Fast Ethernet Controller (FEC) Low-Power Management Module UARTs I 2C The following table compares the two devices described in this document: MCF5207 x MCF5208 x up to 166.67 MHz up to 83.33 MHz up to 159 8 Kbytes 16 Kbytes x -- x 3 x x 4 x 4 x 1 x x x x x x x 3 x x 4 x 4 x 1 x x x x QSPI 32-bit DMA Timers Watchdog Timer (WDT) Periodic Interrupt Timers (PIT) Edge Port Module (EPORT) Interrupt Controllers (INTC) 16-channel Direct Memory Access (DMA) FlexBus External Interface General Purpose I/O Module (GPIO) JTAG - IEEE(R) 1149.1 Test Access Port Package 144 LQFP 160 QFP 144 MAPBGA 196 MAPBGA MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 2 Preliminary Freescale Semiconductor Ordering Information 2 Ordering Information Table 2. Orderable Part Numbers Freescale Part Number MCF5207CAG166 MCF5207CVM166 MCF5208CAB166 MCF5208CVM166 Description MCF5207 RISC Microprocessor, 144 LQFP MCF5207 RISC Microprocessor, 144 MAPBGA MCF5208 RISC Microprocessor, 160 QFP MCF5208 RISC Microprocessor, 196 MAPBGA Speed 166.67 MHz 166.67 MHz 166.67 MHz 166.67 MHz Temperature -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C 3 Signal Descriptions The following table lists all the MCF5208 pins grouped by function. The "Dir" column is the direction for the primary function of the pin only. Refer to Section 4, "Mechanicals and Pinouts," for package diagrams. For a more detailed discussion of the MCF5208 signals, consult the MCF5208 Reference Manual (MCF5208RM). NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A23), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality. Table 3. MCF5207/8 Signal Information and Muxing Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5207 144 LQFP MCF5207 144 MAPBGA MCF5208 160 QFP MCF5208 196 MAPBGA Reset RESET2 RSTOUT -- -- -- -- -- -- I O Clock EXTAL XTAL FB_CLK -- -- -- -- -- -- -- -- -- I O O 78 80 34 K12 J12 L1 86 88 40 L14 K14 N1 82 74 J10 M12 90 82 J14 N14 MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 3 Signal Descriptions Table 3. MCF5207/8 Signal Information and Muxing (continued) Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5207 144 LQFP MCF5207 144 MAPBGA MCF5208 160 QFP MCF5208 196 MAPBGA Mode Selection RCON2 DRAMSEL -- -- -- -- -- -- I I FlexBus A[23:22] A[21:16] -- -- FB_CS[5:4] -- -- -- O O 118, 117 116-114, 112, 108, 107 106, 105 104-102 101 100-91 B9, A10 C9, A11, B10, A12, C11, B11 B12, C12 D11, E10, D12 C10 E11, D9, E12, F10, F11, E9, F12, G10, G12, F9 F1, F2, G1, G2, G4, G3, H1, H2, K3, L2, L3, K2, M3, J4, M4, K4 126, 125 124, 123, 122, 120, 116, 115 114, 113 112, 111, 110 109 108-99 B11, A11 B12, A12, A13, B13, B14, C13 C14, D12 D13, D14, E11 E12 E13, E14, F11-F14, G11-G14 144 79 C4 H10 160 87 C3 K11 A[15:14] A[13:11] A10 A[9:0] -- -- -- -- SD_BA[1:0] SD_A[13:11] -- SD_A[9:0] -- -- -- -- O O O O D[31:16] -- SD_D[31:16]3 -- O 21-28, 40-47 27-34, 46-53 J4-J1, K4-K1, M3, N3, M4, N4, P4, L5, M5, N5 F3-F1, G4-G1, H1, N6, P6, L7, M7, N7, P7, N8, P8 H2, P5, H4, M6 M8 H14 L8 E3 D[15:0] -- FB_D[31:16]3 -- O 8-15, 51-58 B2, B1, C2, C1, D2, D1, E2, E1, L5, K5, L6, J6, M6, J7, L7, K7 20, 48, 18, 50 60 90 59 4 F4, L4, E3, J5 J8 G11 K6 B3 16-23, 57-64 BE/BWE[3:0] OE TA2 R/W TS PBE[3:0] PBUSCTL3 PBUSCTL2 PBUSCTL1 PBUSCTL0 SD_DQM[3:0] -- -- -- DACK0 -- -- -- -- -- O O I O O 26, 54, 24, 56 66 98 65 12 Chip Selects FB_CS[3:2] FB_CS1 FB_CS0 PCS[3:2] PCS1 -- -- SD_CS1 -- -- -- -- O O O 119, 120 121 122 D7, A9 C8 B8 -- 127 128 C11, A10 B10 C10 MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 4 Preliminary Freescale Semiconductor Signal Descriptions Table 3. MCF5207/8 Signal Information and Muxing (continued) Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5207 144 LQFP MCF5207 144 MAPBGA MCF5208 160 QFP MCF5208 196 MAPBGA SDRAM Controller SD_A10 SD_CKE SD_CLK SD_CLK SD_CS0 SD_DQS[3:2] SD_SCAS SD_SRAS SD_SDR_DQS SD_WE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O O O O O O O O O 37 6 31 32 7 19, 49 38 39 29 5 M1 C3 J1 K1 A1 F3, M5 M2 J2 H3 D3 43 14 37 38 15 25, 55 44 45 35 13 N2 E1 L1 M1 F4 H3, L6 P2 P3 L3 E2 External Interrupts Port4 IRQ72 IRQ42 IRQ12 PIRQ72 PIRQ42 PIRQ12 -- DREQ02 -- -- -- -- FEC FEC_MDC FEC_MDIO FEC_TXCLK FEC_TXEN FEC_TXD0 FEC_COL FEC_RXCLK FEC_RXDV FEC_RXD0 FEC_CRS FEC_TXD[3:1] FEC_TXER FEC_RXD[3:1] FEC_RXER PFECI2C3 PFECI2C2 PFECH7 PFECH6 PFECH5 PFECH4 PFECH3 PFECH2 PFECH1 PFECH0 PFECL[7:5] PFECL4 PFECL[3:1] PFECL0 I2C_SCL2 I2C_SDA2 -- -- -- -- -- -- -- -- -- -- -- -- U2TXD U2RXD -- -- -- -- -- -- -- -- -- -- -- -- I2C I2C_SDA2 PFECI2C02 U2RXD2 -- I/O -- -- -- D1 O I/O I O O I I I I I O O I I -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 148 147 157 158 3 7 154 153 152 8 6-4 156 149-151 155 D6 C6 B3 A2 B1 D3 B4 A4 D5 D2 C1, C2, B2 A3 A5, B5, C5 C4 I I I 134 133 132 A5 C6 B6 142 141 140 C7 D7 D8 MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 5 Signal Descriptions Table 3. MCF5207/8 Signal Information and Muxing (continued) Signal Name I2C_SCL2 GPIO PFECI2C12 Alternate 1 U2TXD2 Alternate 2 Dir.1 -- I/O DMA DACK0 and DREQ0 do not have a dedicated bond pads. Please refer to the following pins for muxing: TS and QSPI_CS2 for DACK0, IRQ4 and QSPI_DIN for DREQ0. QSPI QSPI_CS2 QSPI_CLK QSPI_DOUT QSPI_DIN PQSPI3 PQSPI0 PQSPI1 PQSPI2 DACK0 I2C_SCL 2 MCF5207 144 LQFP -- MCF5207 144 MAPBGA -- MCF5208 160 QFP -- MCF5208 196 MAPBGA E4 U2RTS -- -- U2CTS O O O I 126 127 128 129 A8 C7 A7 B7 132 133 134 135 D10 A9 B9 C9 I2C_SDA2 DREQ02 Note: The QSPI_CS1 and QSPI_CS0 signals are available on the U1CTS, U1RTS, U0CTS, or U0RTS pins for the 196 and 160-pin packages. UARTs U1CTS U1RTS U1CTS U1RTS U1TXD U1RXD U0CTS U0RTS U0CTS U0RTS U0TXD U0RXD PUARTL7 PUARTL6 PUARTL7 PUARTL6 PUARTL5 PUARTL4 PUARTL3 PUARTL2 PUARTL3 PUARTL2 PUARTL1 PUARTL0 -- -- DT1IN DT1OUT -- -- -- -- DT0IN DT0OUT -- -- -- -- QSPI_CS1 QSPI_CS1 -- -- -- -- QSPI_CS0 QSPI_CS0 -- -- I O I O O I I O I O O I 139 142 -- -- 131 130 140 141 -- -- 71 70 B4 A2 -- -- A6 D6 E4 D5 -- -- L10 M10 -- -- 136 137 139 138 -- -- 76 77 79 78 -- -- D9 C8 A8 B8 -- -- N12 P12 P13 N13 Note: The UART2 signals are multiplexed on the DMA Timers, QSPI, FEC, and I2C pins. DMA Timers DT3IN DT2IN DT1IN DT0IN PTIMER3 PTIMER2 PTIMER1 PTIMER0 DT3OUT DT2OUT DT1OUT DT0OUT U2CTS U2RTS U2RXD U2TXD I I I I 135 136 137 138 B5 C5 A4 A3 143 144 145 146 B7 A7 A6 B6 BDM/JTAG5 JTAG_EN6 DSCLK -- -- -- TRST2 -- -- I I 83 76 J11 K11 91 84 J13 L12 MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 6 Preliminary Freescale Semiconductor Signal Descriptions Table 3. MCF5207/8 Signal Information and Muxing (continued) Signal Name PSTCLK BKPT DSI DSO DDATA[3:0] PST[3:0] ALLPST GPIO -- -- -- -- -- -- -- Alternate 1 TCLK2 TMS2 TDI 2 Alternate 2 Dir.1 -- -- -- -- -- -- -- Test O I I O O O O MCF5207 144 LQFP 64 75 77 69 -- -- 67 MCF5207 144 MAPBGA M7 L12 H9 M9 K9, L9, M11, M8 L11, L8, K10, K8 -- MCF5208 160 QFP 70 83 85 75 -- -- 73 MCF5208 196 MAPBGA P9 M14 K12 M12 P11, N11, M11, P10 N10, M10, L10, L9 -- TDO -- -- -- TEST6 PLL_TEST -- -- -- -- -- -- I I 109 -- -- -- -- -- C12 M13 Power Supplies EVDD -- -- -- 1, 63, 66, 72, 81, 87, 125 E5-E6, F5, G8-G9, H7-H8 2, 9, 69, 72, E5-E7, F5, 80, 89, 95, F6, G5, H10, 131 J9, J10, K8-K10, K13, M9 36, 74, 92, 121, 159 94 J12, D4, D11, H11, L4, L11, H13 IVDD -- -- -- 30, 68, 84, 113, 143 86 D4, D8, H4, H11, J9 H12 PLL_VDD SD_VDD -- -- -- -- -- -- 3, 17, 33, 35, E7-E8, F8, 11, 39, 41, E8-E10, F9, 61, 89, 110, G5, H5-H6, 67, 97, 118, F10, G10, 123 J3 129 H5, J5, J6, K5-K7, L2 2, 16, 36, 62, D10, F6-F7, 1, 10, 42, 68, 65, 73, 88, G6-G7 71, 81, 96, 111, 124 117, 119, 130 A1, A14, F7-F8, G6-G9, H6-H9, J7-J8, L13, M2, N9, P1, P14 H12 VSS -- -- -- PLL_VSS -- -- -- 85 -- 93 NOTES: 1 Refers to pin's primary function. 2 Pull-up enabled internally on this signal for this mode. 3 Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins. 4 GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 7 Mechanicals and Pinouts 5 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. 6 Pull-down enabled internally on this signal for this mode. 4 Mechanicals and Pinouts NOTE The mechanical drawings are the latest revisions at the time of publication of this document. The most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire. This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5207 and MCF5208 devices. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 8 Preliminary Freescale Semiconductor Mechanicals and Pinouts 4.1 Pinout--144 LQFP QSPI_DOUT QSPI_CLK QSPI_CS2 QSPI_DIN SD_VDD SD_VDD 110 FB_CS0 FB_CS1 FB_CS2 FB_CS3 U1RXD U1RTS U0RTS U0CTS U1CTS U1TXD Figure 1 shows a pinout of the MCF5207CAG166 device. RCON DT0IN DT1IN DT2IN DT3IN EVDD TEST 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 SD_A10 SD_DQS0/2 BE/BWE0 D7 D6 D5 D4 D3 D2 D1 BE/BWE2 D23 D22 D21 D20 D19 D18 D17 D16 D0 TDO/DSO EVDD EVDD TCLK/PSTCLK SD_VDD SD_CAS SD_RAS ALL_PST U0RXD U0TXD EVDD VSS IVDD OE VSS R/W 72 IVDD IVDD IRQ7 IRQ4 IRQ1 VSS 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 EVDD EVSS SD_VDD TS SD_WE SD_CKE SD_CS D15 D14 D13 D12 D11 D10 D9 D8 EVSS SD_VDD BE/BWE1 SD_DQS1/3 BE/BWE3 D31 D30 D29 D28 D27 D26 D25 D24 SD_SDR_DQS IVDD SD_CLK SD_CLK SD_VDD FB_CLK SD_VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 111 * VSS A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 TA SD_VDD VSS EVDD PLL_VDD PLL_VSS IVDD JTAG_EN RESET EVDD XTAL DRAMSEL EXTAL TDI/DSI TRST/DSCLK TMS/BKPT RSTOUT VSS Figure 1. MCF5207CAG166 Pinout Top View (144 LQFP) MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 9 Mechanicals and Pinouts 4.2 Package Dimensions--144 LQFP Figure 2 and Figure 3 show MCF5207CAB166 package dimensions. Figure 2. MCF5207CAB166 Package Dimensions (Sheet 1 of 2) MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 10 Preliminary Freescale Semiconductor Mechanicals and Pinouts View A Rotated 90x CW 144 Places Section A-A View B Figure 3. MCF5207CAB166 Package Dimensions (Sheet 2 of 2) MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 11 Mechanicals and Pinouts 4.3 1 A Pinout--144 MAPBGA 2 U1RTS 3 DT0IN 4 DT1IN 5 IRQ7 6 U1TXD 7 QSPI_ DOUT 8 QSPI_CS2 9 FB_CS2 10 A22 11 A20 12 A18 A The pinout of the MCF5207CVM166 device is shown below. SD_CS B D14 D15 TS U1CTS DT3IN IRQ1 QSPI_DIN FB_CS0 A23 A19 A16 A15 B C D12 D13 SD_CKE RCON DT2IN IRQ4 QSPI_ CLK FB_CS1 A21 A10 A17 A14 C D D10 D11 SD_WE IVDD U0RTS U1RXD FB_CS3 IVDD A8 VSS A13 A11 D E D8 D9 BE/BWE1 U0CTS EVDD EVDD SD_VDD SD_VDD A4 A12 A9 A7 E F D31 D30 SD_DQS1 BE/BWE3 EVDD VSS VSS SD_VDD A0 A6 A5 A3 F G D29 D28 D26 D27 SD_VDD VSS VSS EVDD EVDD A2 TA A1 G H D25 D24 SD_SDR_ DQS IVDD SD_VDD SD_VDD EVDD EVDD TDI/DSI DRAM SEL IVDD PLL_VDD H J SD_CLK SD_RAS SD_VDD D18 BE/BWE0 D4 D2 OE IVDD RESET JTAG_EN XTAL J K SD_CLK D20 D23 D16 D6 R/W D0 PST0 DDATA3 PST1 TRST/ DSCLK EXTAL K L FB_CLK D22 D21 BE/BWE2 D7 D5 D1 PST2 DDATA2 U0TXD PST3 TMS/ BKPT L M SD_A10 1 SD_CAS 2 D19 3 D17 4 SD_DQS0 5 D3 6 TCLK/ PSTCLK 7 DDATA0 8 TDO/DSO 9 U0RXD 10 DDATA1 11 RSTOUT 12 M Figure 4. MCF5207CVM166 Pinout Top View (144 MAPBGA) MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 12 Preliminary Freescale Semiconductor Mechanicals and Pinouts 4.4 Package Dimensions--144 MAPBGA Figure 5 shows the MCF5207CAB166 package dimensions. Figure 5. MCF5207CAB166 Package Dimensions (144 MAPBGA) MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 13 Mechanicals and Pinouts 4.5 Pinout--160 QFP FEC_RXCLK QSPI_DOUT FEC_TXCLK FEC_RXER FEC_RXDV FEC_RXD0 FEC_RXD1 FEC_RXD2 FEC_RXD3 FEC_TXEN FEC_TXER FEC_MDIO QSPI_CLK QSPI_CS2 FEC_MDC QSPI_DIN SD_VDD FB_CS0 FB_CS1 U1RXD U1RTS U1CTS U1TXD Figure 6 shows a pinout of the MCF5208CAB166 device. RCON DT0IN DT1IN DT2IN DT3IN EVDD IVDD IVDD 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 SD_A10 SD_DQS0/2 BE/BWE2 BE/BWE0 D23 D22 D21 D20 D19 D18 D17 D16 D7 D6 D5 D4 D3 D2 D1 D0 TDO/DSO EVDD EVDD TCLK/PSTCLK SD_VDD SD_VDD SD_CAS SD_RAS ALL_PST U0RXD U0TXD U0CTS U0RTS EVDD VSS IVDD VSS OE VSS R/W 80 IRQ7 IRQ4 IRQ1 VSS A23 A22 A21 A20 123 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 VSS EVDD FEC_TXD0 FEC_TXD1 FEC_TXD2 FEC_TXD3 FEC_COL FEC_CRS EVDD VSS SD_VDD TS SD_WE SD_CKE SD_CS D15 D14 D13 D12 D11 D10 D9 D8 BE/BWE1 SD_DQS1/3 BE/BWE3 D31 D30 D29 D28 D27 D26 D25 D24 SD_SDR_DQS IVDD SD_CLK SD_CLK SD_VDD FB_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 122 * A19 A18 VSS SD_VDD VSS A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 TA SD_VDD VSS EVDD PLL_VDD PLL_VSS IVDD JTAG_EN RESET EVDD XTAL DRAMSEL EXTAL TDI/DSI TRST/DSCLK TMS/BKPT RSTOUT VSS Figure 6. MCF5208CAB166 Pinout Top View (160 QFP) MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 14 Preliminary Freescale Semiconductor Mechanicals and Pinouts 4.6 Package Dimensions--160 QFP The package dimensions of the MCF5208CAB166 device are shown in the figures below. Top View Figure 7. MCF5208CAB166 Package Dimensions (Sheet 1 of 2) MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 15 Mechanicals and Pinouts SECTION B-B DETAIL A Figure 8. MCF5208CAB166 Package Dimensions (Sheet 2 of 2) MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 16 Preliminary Freescale Semiconductor Mechanicals and Pinouts 4.7 1 A VSS Pinout--196 MAPBGA 2 FEC_ TXEN FEC_ TXD1 FEC_ TXD2 FEC_ CRS 3 FEC_ TXER FEC_ TXCLK 4 FEC_ RXDV FEC_ RXCLK FEC_ RXER 5 FEC_ RXD3 FEC_ RXD2 FEC_ RXD1 FEC_ RXD0 6 DT1IN 7 DT2IN 8 U1TXD 9 QSPI_ CLK QSPI_ DOUT QSPI_ DIN 10 FB_CS2 11 A22 12 A20 13 A19 14 VSS A Figure 6 shows a pinout of the MCF5208CVM166 device. B FEC_ TXD0 FEC_ TXD3 DT0IN DT3IN U1RXD FB_CS1 A23 A21 A18 A17 B C RCON FEC_ MDIO FEC_ MDC IRQ7 U1RTS FB_CS0 FB_CS3 TEST A16 A15 C D I2C_SDA FEC_ COL IVDD IRQ4 IRQ1 U1CTS QSPI_ CS2 IVDD A14 A13 A12 D E SD_CKE SD_WE TS I2C_SCL EVDD EVDD EVDD SD_VDD SD_VDD SD_VDD A11 A10 A9 A8 E F D13 D14 D15 SD_CS EVDD EVDD VSS VSS SD_VDD SD_VDD A7 A6 A5 A4 F G D9 D10 D11 D12 EVDD VSS VSS VSS VSS SD_VDD A3 A2 A1 A0 G H D8 BE/ BWE3 SD_ DQS1 BE/ BWE1 SD_VDD VSS VSS VSS VSS EVDD IVDD PLL_ VSS PLL_ VDD JTAG_ EN TA H J D28 D29 D30 D31 SD_VDD SD_VDD VSS VSS EVDD EVDD NC IVDD RESET J K D24 D25 D26 D27 SD_VDD SD_VDD SD_VDD EVDD EVDD EVDD DRAM SEL TDI/ DSI TRST/ DSCLK TDO/ DSO EVDD XTAL K L SD_CLK SD_VDD SD_DR_ DQS IVDD D18 SD_ DQS0 BE/ BWE0 D5 R/W PST0 PST1 IVDD VSS EXTAL L M SD_CLK VSS D23 D21 D17 D4 OE EVDD PST2 DDATA1 PLL_ TEST TMS/ BKPT M N FB_CLK SD_A10 D22 D20 D16 D7 D3 D1 VSS PST3 DDATA2 U0CTS U0RXD RSTOUT N P VSS 1 SD_CAS SD_RAS 2 3 D19 4 BE/ BWE2 5 D6 6 D2 7 D0 8 TCLK/ PSTCLK 9 DDATA0 10 DDATA3 11 U0RTS 12 U0TXD 13 VSS 14 P Figure 9. MCF5208CVM166 Pinout Top View (196 MAPBGA) MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 17 Preliminary Electrical Characteristics 4.8 Package Dimensions--196 MAPBGA The package dimensions for the MCF5208CVM166 device is shown below. Top View Bottom View Figure 10. MCF5208CVM166 Package Dimensions (196 MAPBGA) 5 Preliminary Electrical Characteristics The following electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. 5.1 Maximum Ratings Table 4. Absolute Maximum Ratings1, 2 Rating Core Supply Voltage CMOS Pad Supply Voltage DDR/Memory Pad Supply Voltage PLL Supply Voltage Symbol IVDD EVDD SDVDD PLLVDD Value - 0.5 to +2.0 - 0.3 to +4.0 - 0.3 to +4.0 - 0.3 to +2.0 Unit V V V V MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 18 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics Table 4. Absolute Maximum Ratings1, 2 (continued) Digital Input Voltage 3 Instantaneous Maximum Current Single pin limit (applies to all pins) 3, 4, 5 Operating Temperature Range (Packaged) Storage Temperature Range VIN ID TA (TL - TH) Tstg - 0.3 to +3.6 25 - 40 to 85 - 55 to 150 V mA C C NOTES: 1 Functional operating conditions are given in Section 5.4, "DC Electrical Specifications." Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. 2 This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or EVDD). 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 All functional non-supply pins are internally clamped to V SS and EVDD. 5 Power supply must maintain regulation within operating EV DD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > EVDD is greater than IDD, the injection current may flow out of EVDD and could result in external power supply going out of regulation. Insure external EVDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no clock). Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions. 5.2 Thermal Characteristics Table 5. Thermal Characteristics Characteristic Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature Four layer board (2s2p) Four layer board (2s2p) Symbol JMA JMA JB JC jt Tj 196MBGA 321,2 291,2 203 104 21,5 105 160QFP 401,2 361,2 253 104 21,5 105 Unit C/W C/W C/W C/W C/W oC Table 5 lists thermal resistance values MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 19 Preliminary Electrical Characteristics NOTES: 1 JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-6 with the board horizontal. 3 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D x JMA ) Eqn. 1 Where: TA QJMA PD PINT PI/O = Ambient Temperature, C = Package Thermal Resistance, Junction-to-Ambient, xC/W = PINT + PI/O = IDD x IVDD, Watts - Chip Internal Power = Power Dissipation on Input and Output Pins -- User Determined For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: K P D = -------------------------------( T J + 273C ) Eqn. 2 Solving equations 1 and 2 for K gives: K = P D x ( T A x 273C ) + Q JMA x P D 2 Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 5.3 ESD Protection Table 6. ESD Protection Characteristics1, 2 Characteristics ESD Target for Human Body Model Symbol HBM Value 2000 Units V MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 20 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics NOTES: 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 5.4 DC Electrical Specifications Table 7. DC Electrical Specifications Characteristic Core Supply Voltage PLL Supply Voltage CMOS Pad Supply Voltage Mobile DDR/Bus Pad Supply Voltage DDR/Bus Pad Supply Voltage SDR/Bus Pad Supply Voltage CMOS Input High Voltage CMOS Input Low Voltage Mobile DDR/Bus Input High Voltage Mobile DDR/Bus Input Low Voltage DDR/Bus Input High Voltage DDR/Bus Input Low Voltage Input Leakage Current Vin = IVDD or VSS, Input-only pins CMOS Output High Voltage IOH = -5.0 mA CMOS Output Low Voltage IOL = 5.0 mA DDR/Bus Output High Voltage IOH = -5.0 mA DDR/Bus Output Low Voltage IOL = 5.0 mA Weak Internal Pull Up Device Current, tested at VIL Max.1 Symbol IVDD PLLVDD EVDD SDVDD SDVDD SDVDD EVIH EVIL SDVIH SDVIL SDVIH SDVIL Iin EVOH EVOL SDVOH SDVOL IAPU Min 1.4 1.4 3.0 1.65 2.25 3.0 2 -0.05 TBD -0.05 2 -0.05 -1.0 EVDD - 0.4 -- SDVDD - 0.4 -- -10 Max 1.6 1.6 3.6 1.95 2.75 3.6 EVDD + 0.05 0.8 SDVDD + 0. 05 TBD SDVDD + 0. 05 0.8 1.0 -- 0.4 -- 0.4 - 130 Unit V V V V V V V V V V V V A V V V V A MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 21 Preliminary Electrical Characteristics Table 7. DC Electrical Specifications (continued) Characteristic Input Capacitance 2 All input-only pins All input/output (three-state) pins Core Operating Supply Current 3 Master Mode LIMP mode STOP mode Low Power mode 1 Symbol Cin Min Max Unit pF -- -- IDD -- 7 7 170 TBD 1 TBD mA mA mA mA NOTES: Refer to the signals section for pins having weak internal pull-up devices. 2 This parameter is characterized before qualification rather than 100% tested. 3 Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. 5.4.1 PLL Power Filtering To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 11 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible. 10 Board VDD 10 F 0.1 F PLL VDD Pin GND Figure 11. System PLL VDD Power Filter 5.4.2 Supply Voltage Sequencing and Separation Cautions Figure 12 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD (PLLVDD), and Core VDD (IVDD). MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 22 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics DC Power Supply Voltage 3.3V Supplies Stable 2.5V EVDD, SDVDD SDVDD (2.5V/1.8V) 1.5V 1 IVDD, PLLVDD 2 0 Time Notes: 1. IVDD should not exceed EVDD, SDVDD or PLLVDD by more than 0.4 V at any time, including power-up. 2. Recommended that IVDD/PLLVDD should track EVDD/SDVDD up to 0.9 V, then separate for completion of ramps. 3. Input voltage must not be greater than the supply voltage (EVDD, SDVDD, IVDD, or PLLVDD) by more than 0.5 V at any time, including during power-up. 4. Use 1 s or slower rise time for all supplies. Figure 12. Supply Voltage Sequencing and Separation Cautions The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. Both SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD. 5.4.2.1 Power Up Sequence If EVDD/SDVDD are powered up with IVDD at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD, SDVDD or PLLVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 s to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: 1. Use 1 s or slower rise time for all supplies. 2. IVDD/PLLVDD and EVDD/SDVDD should track up to 0.9 V, then separate for the completion of ramps with EVDD/SD VDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator. 5.4.2.2 Power Down Sequence If IVDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 23 Preliminary Electrical Characteristics than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop IVDD/PLLVDD to 0 V. 2. Drop EVDD/SDVDD supplies. 5.5 Oscillator and PLL Electrical Characteristics Table 8. PLL Electrical Characteristics Num 1 Characteristic PLL Reference Frequency Range Crystal reference External reference Core frequency CLKOUT Frequency 1 Crystal Start-up Time 2, 3 EXTAL Input High Voltage Crystal Mode4 All other modes (External, Limp) EXTAL Input Low Voltage Crystal Mode4 All other modes (External, Limp) XTAL Load Capacitance2 PLL Lock Time 2,5 Duty Cycle of reference2 tlpll tdc Symbol Min. Value Max. Value Unit fref_crystal fref_ext fsys fsys/2 t cst TBD TBD TBD TBD -- TBD TBD TBD TBD 5 -- 40 16 16 166.67 83.33 10 TBD TBD TBD TBD 30 1 60 MHz MHz MHz MHZ ms V V V V pF ms % 2 3 4 VIHEXT VIHEXT VILEXT VILEXT 5 6 11 14 NOTES: 1 All internal registers retain data at 0 Hz. 2 This parameter is guaranteed by characterization before qualification rather than 100% tested. 3 Proper PC board layout procedures must be followed to achieve specifications. 4 This parameter is guaranteed by design rather than 100% tested. 5.6 External Interface Timing Characteristics NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the FB_CLK output. All other timing relationships can be derived from these values.Timings listed in Table 9 are shown in Figure 14 & Figure 15. Table 9 lists processor bus input timings. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 24 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics * The timings are also valid for inputs sampled on the negative clock edge. FB_CLK(75MHz) TSETUP THOLD 1.5V Valid 1.5V 1.5V Input Setup And Hold Invalid Invalid trise Input Rise Time Vh = VIH Vl = VIL Input Fall Time Vh = VIH Vl = VIL tfall FB_CLK FB4 FB5 Inputs Figure 13. General Input Timing Requirements 5.6.1 FlexBus A multi-function external bus interface called FlexBus is provided to interface to slave-only devices up to a maximum bus frequency of 83.33 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, Flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces. Chip-select FB_CS[0] can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM/Flash memories. 5.6.1.1 FlexBus AC Timing Characteristics The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock. Table 9. FlexBus AC Timing Specifications Num Characteristic Frequency of Operation FB1 Clock Period (FB_CLK) tFBCK Symbol Min Max 83.33 12 Unit Mhz ns Notes fsys/2 tcyc MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 25 Preliminary Electrical Characteristics Table 9. FlexBus AC Timing Specifications Num FB2 FB3 FB4 FB5 FB6 FB7 FB8 FB9 Characteristic Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE) Data, and Control Output Hold ((A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE) Data Input Setup Data Input Hold Transfer Acknowledge (TA) Input Setup Transfer Acknowledge (TA) Input Hold Address Output Valid (A[23:0]) Address Output Hold (A[23:0]) Symbol tFBCHDCV tFBCHDCI tDVFBCH tDIFBCH tCVFBCH tCIFBCH tFBCHAV tFBCHAI Min -- 1 3.5 0 4 0 -- 1.0 Max 7.0 -- -- -- -- -- 6.0 -- Unit ns ns ns ns ns ns ns ns 3 Notes 1 1, 2 NOTES: 1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7, "SDRAM BUS" for SD_CS[1:0] timing. 2 The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for more information. 3 These specs are used when the A[23:0] signals are configured as 23-bit, non-muxed FlexBus address signals. FB_CLK FB1 FB9 A[23:0] FB8 A[23:0] FB5 D[31:0] FB2 DATA R/W FB4 TS FB_CSn, BE/BWEn FB7 OE FB6 TA Figure 14. FlexBus Read Timing MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 26 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics FB_CLK FB1 FB9 A[23:0] FB8 FB3 D[31:0] FB2 R/W TS FB_CSn, BE/BWEn FB7 OE FB6 TA Figure 15. Flexbus Write Timing 5.7 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable for either Class I or Class II drive strength. 5.7.1 SDR SDRAM AC Timing Characteristics The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the device for each data beat of an SDR read. The ColdFire processor accomplishes this by asserting a signal called SD_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal and its usage. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 27 Preliminary Electrical Characteristics Table 10. SDR Timing Specifications Symbol Characteristic Frequency of Operation SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 Clock Period (tCK) Clock Skew (tSK) Pulse Width High (tCKH) Pulse Width Low (tCKL) Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Valid (tCMV) Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Hold (tCMH) SD_SDR_DQS Output Valid (tDQSOV) tSDCK tSDSK tSDCKH tSDCKL tSDCHACV tSDCHACI tDQSOV Symbol Min -- 7.52 -- 0.45 0.45 -- 2.0 -- Max 83.33 12 TBD 0.55 0.55 0.5 x SD_CLK + 1.0 -- Self timed SD_CLK SD_CLK ns ns ns ns 4 5 6 7 3 3 Unit MHz ns Notes 1 2 SD_DQS[3:0] input setup relative to SD_CLK (tDQSIS) tDQVSDCH 0.25 x SD_CLK 0.40 x SD_CLK SD_DQS[3:2] input hold relative to SD_CLK (tDQSIH) Data (D[31:0]) Input Setup relative to SD_CLK (reference only) (tDIS) Data Input Hold relative to SD_CLK (reference only) (tDIH) Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid (tDV) Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold (tDH) tDQISDCH tDVSDCH tDISDCH tSDCHDMV tSDCHDMI Does not apply. 0.5 SD_CLK fixed width. 0.25 x SD_CLK 1.0 -- 1.5 -- -- 0.75 x SD_CLK + 0.5 -- ns ns ns ns NOTES: 1 The device supports the same frequency of operation for both FlexBus and SDRAM as that of the internal bus clock. Please see the PLL chapter of the MCF5208 Reference Manual for more information on setting the SDRAM clock rate. 2 SD_CLK is one SDRAM clock in (ns). 3 Pulse width high plus pulse width low cannot exceed min and max clock period. 4 SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat. 5 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data beat. 6 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller. 7 Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is just provided as guidance. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 28 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics SD2 SD_CLK0 SD1 SD3 SD2 SD_CLK1 SD4 SD6 SD_CSn, SD_RAS, SD_CAS SD_WE, A[23:0], SD_BA[1:0] CMD SD5 ROW COL SD12 SDDM SD13 D[31:0] WD1 WD2 WD3 WD4 Figure 16. SDR Write Timing MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 29 Preliminary Electrical Characteristics SD2 SD_CLK0 SD1 SD2 SD_CLK1 SD_CSn, SD_RAS, SD_CAS, SD_WE SD6 CMD SD5 3/4 MCLK Reference ROW COL tDQS A[23:0], SD_BA[1:0] SDDM SD7 SD_DQS (Measured at Output Pin) Board Delay SD9 SD_DDQS (Measured at Input Pin) Board Delay SD8 Delayed SD_CLK SD10 D[31:0] form Memories WD1 NOTE: Data driven from memories relative to delayed memory clock. SD11 WD2 WD3 WD4 Figure 17. SDR Read Timing 5.7.2 DDR SDRAM AC Timing Characteristics When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early board design. Please contact your local Freescale representative if questions develop. Table 11. DDR Timing Specifications Num Characteristic Frequency of Operation DD1 DD2 DD3 DD4 Clock Period (SD_CLK) Pulse Width High Pulse Width Low Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Valid tDDCK tDDCKH tDDCKL tSDCHACV Symbol Min 83.33 TBD 0.45 0.45 -- Max TBD 12 0.55 0.55 0.5 x SD_CLK + 1.0 Unit Mhz ns SD_CLK SD_CLK ns Notes 1 2 3 3 4 MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 30 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics Table 11. DDR Timing Specifications (continued) Num DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 Characteristic Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Hold Write Command to first DQS Latching Transition Data and Data Mask Output Setup (DQ-->DQS) Relative to DQS (DDR Write Mode) Data and Data Mask Output Hold (DQS-->DQ) Relative to DQS (DDR Write Mode) Input Data Skew Relative to DQS (Input Setup) Input Data Hold Relative to DQS. DQS falling edge from SDCLK rising (output hold time) DQS input read preamble width (tRPRE) DQS input read postamble width (tRPST) DQS output write preamble width (tWPRE) DQS output write postamble width (tWPST) Symbol tSDCHACI tCMDVDQ tDQDMV tDQDMI tDVDQ tDIDQ tDQLSDCH tDQRPRE tDQRPST tDQWPRE tDQWPST 1.5 1.0 -- 0.25 x SD_CLK + 0.5ns 0.5 0.9 0.4 0.25 0.4 Min 2.0 Max -- 1.25 -- -- 1 -- -- 1.1 0.6 -- 0.6 Unit ns SD_CLK ns ns ns ns ns SD_CLK SD_CLK SD_CLK SD_CLK 5 6 7 Notes 8 9 NOTES: 1 The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same frequency as the internal bus clock. 2 SD_CLK is one SDRAM clock in (ns). 3 Pulse width high plus pulse width low cannot exceed min and max clock period. 4 Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and voltage variations. 5 This specification relates to the required input setup time of today's DDR memories. The device's output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. 6 The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats will be valid for each subsequent DQS edge. 7 This specification relates to the required hold time of today's DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. 8 Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 9 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 31 Preliminary Electrical Characteristics DD1 SD_CLK DD2 DD3 SD_CLK DD5 SD_CSn, SD_WE, SD_RAS, SD_CAS DD4 A[13:0] CMD DD6 ROW COL DD7 DM3/DM2 DD8 SD_DQS3/SD_DQS2 DD7 D[31:24]/D[23:16] WD1 WD2 WD3 WD4 DD8 Figure 18. DDR Write Timing MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 32 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics DD1 SD_CLK DD2 DD3 SD_CLK DD5 SD_CSn, SD_WE, SD_RAS, SD_CAS DD4 A[13:0] CL=2 CMD CL=2.5 ROW COL DQS Read Preamble DD10 DD9 SD_DQS3/SD_DQS2 CL = 2 DQS Read Postamble D[31:24]/D[23:16] SD_DQS3/SD_DQS2 CL = 2.5 WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble D[31:24]/D[23:16] WD1 WD2 WD3 WD4 Figure 19. DDR Read Timing Figure 20 shows the DDR clock crossover specifications. SD_CLK VIX VMP VIX SD_CLK VID Figure 20. DDR Clock Crossover Timing 5.8 General Purpose I/O Timing Table 12. GPIO Timing1 Num G1 G2 G3 G4 Characteristic FB_CLK High to GPIO Output Valid FB_CLK High to GPIO Output Invalid GPIO Input Valid to FB_CLK High FB_CLK High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 8 1.5 Max 8 -- -- -- Unit ns ns ns ns MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 33 Preliminary Electrical Characteristics NOTES: 1 GPIO spec cover: IRQn, UART and Timer pins. FB_CLK G1 GPIO Outputs G2 G3 GPIO Inputs G4 Figure 21. GPIO Timing 5.9 Num R1 R2 R3 R4 R5 R6 R7 R8 Reset and Configuration Override Timing Table 13. Reset and Configuration Override Timing Characteristic RESET Input valid to FB_CLK High FB_CLK High to RESET Input invalid RESET Input valid Time 1 FB_CLK High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ Min 9 1.5 5 -- 0 20 0 -- Max -- -- -- 10 -- -- -- 1 Unit ns ns tCYC ns ns tCYC ns tCYC NOTES: 1 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns. FB_CLK R1 R3 RESET R2 R4 RSTOUT R4 R8 R5 Configuration Overrides*: (RCON, Override pins) R6 R7 Figure 22. RESET and Configuration Override Timing MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 34 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics NOTE Refer to the MCF5208 Reference Manual for more information. 5.10 I2C Input/Output Timing Specifications Table 14 and Table 15 list specifications for the I2C input and output timing parameters. Table 14. I2C Input Timing Specifications between I2C_SCL and I2C_SDA Num I1 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 8 -- 0 -- 4 0 2 2 Max -- -- 1 -- 1 -- -- -- -- Units tcyc tcyc ms ns ms tcyc ns tcyc tcyc Table 15. I2C Output Timing Specifications between I2C_SCL and I2C_SDA Num I11 I2 1. Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 6 10 -- 7 -- 10 2 20 10 Max -- -- -- -- 3 -- -- -- -- Units tcyc tcyc s tcyc ns tcyc tcyc tcyc tcyc I3 2 I4 1. I5 3 I6 1. I7 1. I8 1. I9 1. NOTES: 1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table A-16. The I2C interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table A-16 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 35 Preliminary Electrical Characteristics I2 I2C_SCL I6 I5 I1 I4 I7 I8 I3 I9 I2C_SDA Figure 23. I2C Input/Output Timings 5.11 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. 5.11.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV, FEC_RXER, and FEC_RXCLK) The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_RXCLK frequency. Table 16 lists MII receive channel timings. Table 16. MII Receive Signal Timing Num M1 M2 M3 M4 Characteristic FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold FEC_RXCLK pulse width high FEC_RXCLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns FEC_RXCLK period FEC_RXCLK period Figure 24 shows MII receive signal timings listed in Table 16. M3 FEC_RXCLK (input) M4 FEC_RXD[3:0] (inputs) FEC_RXDV FEC_RXER M1 M2 Figure 24. MII Receive Signal Timing Diagram MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 36 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics 5.11.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK) Table 17 lists MII transmit channel timings. The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_TXCLK frequency. The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for details of this option and how to enable it. Table 17. MII Transmit Signal Timing Num M5 M6 M7 M8 Characteristic FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid FEC_TXCLK pulse width high FEC_TXCLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns FEC_TXCLK period FEC_TXCLK period Figure 25 shows MII transmit signal timings listed in Table 17. M7 FEC_TXCLK (input) M5 FEC_TXD[3:0] (outputs) FEC_TXEN FEC_TXER M6 M8 Figure 25. MII Transmit Signal Timing Diagram 5.11.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL) Table 18 lists MII asynchronous inputs signal timing. Table 18. MII Async Inputs Signal Timing Num M9 Characteristic FEC_CRS, FEC_COL minimum pulse width Min 1.5 Max -- Unit FEC_TXCLK period Figure 26 shows MII asynchronous input timings listed in Table 18. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 37 Preliminary Electrical Characteristics FEC_CRS FEC_COL M9 Figure 26. MII Async Inputs Timing Diagram 5.11.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC) Table 19 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 19. MII Serial Management Channel Timing Num Characteristic Min 0 -- 10 0 Max -- 25 -- -- Unit ns ns ns ns M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay) M12 FEC_MDIO (input) to FEC_MDC rising edge setup M13 FEC_MDIO (input) to FEC_MDC rising edge hold M14 FEC_MDC pulse width high M15 FEC_MDC pulse width low 40% 60% FEC_MDC period 40% 60% FEC_MDC period Figure 27 shows MII serial management channel timings listed in Table 19. M14 M15 FEC_MDC (output) M10 FEC_MDIO (output) M11 FEC_MDIO (input) M12 M13 Figure 27. MII Serial Management Channel Timing Diagram MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 38 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics 5.12 32-Bit Timer Module AC Timing Specifications Table 20 lists timer module AC timings. Table 20. Timer Module AC Timing Specifications Name Characteristic Min T1 T2 DT0IN / DT1IN / DT2IN / DT3IN cycle time DT0IN / DT1IN / DT2IN / DT3IN pulse width 3 1 Max -- -- tCYC tCYC Unit 5.13 QSPI Electrical Specifications Table 21 lists QSPI timings. Table 21. QSPI Modules AC Timing Specifications Name QS1 QS2 QS3 QS4 QS5 QSPI_CS[3:0] to QSPI_CLK QSPI_CLK high to QSPI_DOUT valid. QSPI_CLK high to QSPI_DOUT invalid. (Output hold) QSPI_DIN to QSPI_CLK (Input setup) QSPI_DIN to QSPI_CLK (Input hold) Characteristic Min 1 -- 1.5 9 9 Max 510 10 -- -- -- Unit tcyc ns ns ns ns The values in Table 21 correspond to Figure 28. QS1 QSPI_CS[3:0] QSPI_CLK QS2 QSPI_DOUT QS3 QSPI_DIN QS4 QS5 Figure 28. QSPI Timing MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 39 Preliminary Electrical Characteristics 5.14 JTAG and Boundary Scan Timing Table 22. JTAG and Boundary Scan Timing Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 4 26 0 4 26 0 0 4 10 0 0 100 10 Max 1/4 -- -- 3 -- -- 33 33 -- -- 26 8 -- -- Unit fsys/2 tCYC ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1 JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it. J2 J3 VIH J4 VIL J4 J3 TCLK (input) Figure 29. Test Clock Input Timing MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 40 Preliminary Freescale Semiconductor Preliminary Electrical Characteristics TCLK VIL J5 VIH J6 Data Inputs J7 Input Data Valid Data Outputs J8 Output Data Valid Data Outputs J7 Data Outputs Output Data Valid Figure 30. Boundary Scan (JTAG) Timing TCLK VIL J9 VIH J10 TDI TMS J11 Input Data Valid TDO J12 Output Data Valid TDO J11 TDO Output Data Valid Figure 31. Test Access Port Timing TCLK J14 TRST J13 Figure 32. TRST Timing 5.15 Debug AC Timing Specifications Table 23 lists specifications for the debug AC timing parameters shown in Figure 33 & Figure 34. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 41 Preliminary Electrical Characteristics Table 23. Debug AC Timing Specification Num Characteristic Min DE0 DE1 DE2 DE3 DE4 DE5 1 DE6 DE7 PSTCLK cycle time PST valid to PSTCLK high PSTCLK high to PST invalid DSCLK cycle time DSI valid to DSCLK high DSCLK high to DSO invalid BKPT input data setup time to FB_CLK high FB_CLK high to BKPT invalid -- 2 1 5 1 4 4 0 Max 0.5 -- -- -- -- -- -- -- tcyc ns ns tcyc tcyc tcyc ns ns Units NOTES: 1 DSCLK and DSI are synchronized internally. DE4 is measured from the synchronized DSCLK input relative to the rising edge of FB_CLK. Figure 33 shows real-time trace timing for the values in Table 23. PSTCLK DE0 DE1 DE2 PST[3:0] DDATA[3:0] Figure 33. Real-Time Trace AC Timing Figure 34 shows BDM serial port AC timing and BKPT pin timing for the values in Table 23. MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 42 Preliminary Freescale Semiconductor Revision History FB_CLK DE6 BKPT DE7 DE5 DSCLK DE3 DSI Current DE4 Next DSO Past Current Figure 34. BDM Serial Port AC Timing 6 Revision History Table 24. Revision History Revision Number 0 0.1 Date 5/23/2005 6/16/2005 * Initial Release * Corrected 144QFP pinout in Figure 1. Pins 139-142 incorrectly showed FEC functionality, which are actually UART 0/1 clear-to-send and request-to-send signals. * Changed maximum core frequency in Table 8, spec #2, from 240MHz to 166.67MHz. Also, changed symbols in table: fcore -> fsys and fsys -> fsys/2 for consistency throughout document and reference manual. Substantive Changes MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 43 Revision History Table 24. Revision History (continued) Revision Number 0.2 Date 8/26/2005 Substantive Changes * Changed ball M9 from SD_VDD to EVDD in Figure 9. * Table 3: Pin 33 for 144 LQFP package should be EVDD instead of SD_VDD. BE/BWE[3:0] for 144 LQFP should be "20, 48, 18, 50" instead of "18, 20, 48, 50" Cleaned up various electrical specifications: * Table 4: Added DDR/Memory pad supply voltage spec, changed "clock synthesizer supply voltage" to "PLL supply voltage", changed min PLLVDD from -0.5 to -0.3, changed max VIN from 4.0 to 3.6, changed minimum Tstg from -65 to -55, * Table 5: Changed TBD values in Tj entry to 105C. * Table 7: Changed minimum core supply voltage from 1.35 to 1.4 and maximum from 1.65 to 1.6, added PLL supply voltage entry, added pad supply entries for mobile-DDR, DDR, and SDR, changed minimum input high voltage from 0.7xEVDD to 2 and maximum from 3.65 to EVDD+0.05, changed minimum input low voltage from VSS-0.3 to -0.05 and maximum from 0.35xEVDDto 0.8, added input high/low voltage entries for DDR and mobile-DDR, removed high impedance leakage current entry, changed minimum output high voltage from EVDD-0.5 to EVDD-0.4, added DDR/bus output high/low voltage entries, removed load capacitance and DC injection current entries. * Added filtering circuits and voltage sequencing sections: Section 5.4.1, "PLL Power Filtering," and Section 5.4.2, "Supply Voltage Sequencing and Separation Cautions." * Removed "Operating Conditions" table from Section 5.5, "Oscillator and PLL Electrical Characteristics," since it is redundant with Table 7. * Table 9: Changed minimum core frequency to TBD, removed external reference and on-chip PLL frequency specs to have only a CLKOUT frequency spec of TBD to 83.33MHz, removed loss of reference frequency and self-clocked mode frequency entries, in EXTAL input high/low voltage entries changed "All other modes (Dual controller (1:1), Bypass, External)" to "All other modes (External, Limp)", removed XTAL output high/low voltage entries, removed power-up to lock time entry, removed last 5 entries (frequency un-lock range, frequency lock range, CLKOUT period jitter, frequency modulation range limit, and ICO frequency) * * * * Corrected DRAMSEL footnote #3 in Table 3. Updated Table 3 with 144MAPBGA pin locations. Added 144MAPBGA ballmap to Section 4.3, "Pinout--144 MAPBGA." Changed J12 from PLL_VDD to IVDD in Figure 9. 0.3 9/07/2005 0.4 10/10/2005 * Figure 1 and Table 3: Changed pin 33 from EVDD to SD_VDD * Figure 4 and Table 3: Changed ball D10 from TEST to VSS * Figure 6 and Table 3: Changed pin 39 from EVDD to SD_VDD and pin 117 from TEST to VSS * Added "top view" and "bottom view" labels where appropriate to mechanical drawings and pinouts. * Updated mechanical drawings to latest available, and added note to Section 4, "Mechanicals and Pinouts." 0.5 3/29/2006 MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 44 Preliminary Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK MCF5208 ColdFire(R) Microprocessor Data Sheet, Rev. 0.5 Freescale Semiconductor Preliminary 45 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.(c) Freescale Semiconductor, Inc. 2006. All rights reserved. MCF5208EC Rev. 0.5 3/2006 |
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